The present invention relates to a real-time processor debug system, and more particularly to a debug system that selectively samples address and data signals of a virtual bus of a core processor during real-time operation to reduce power consumption and to minimize performance impact due to bus loading.
Embedded systems that contain a core processor, on-chip memory and an external memory interface module are commonplace. Current generation systems are integrating cache memories as well. System level code developers must write software or application code for the embedded systems to perform the particular functions necessary for the system. Most software must be revised several times by developers for various reasons, including adding or revising functionality, removing undesired features, and removing xe2x80x9cbugsxe2x80x9d or software errors. Thus, it is necessary during application code development to debug the software to ensure proper operation. The application code of an embedded system may further require ongoing, constant or periodic adjustment during operation. In some configurations, certain parameters, characteristic values or tables of constants may need adjustment or modification during real-time operation. The debug process as referred to herein includes initial application code development as well as real-time calibration or adjustment functions during operation.
Some legacy systems, including systems without a cache memory, provide the core processor bus externally so that core processor cycles are readily available for purposes of debugging. System level debug becomes more difficult in an embedded system environment with a cache memory since the pin or bus visibility of the core processor is no longer available. In particular, a cache memory is often positioned between the embedded core processor and the external physical bus so that the core processor bus is not externally available. For example, xe2x80x9cshow cyclexe2x80x9d support is not an option as it was in prior embedded systems that did not have cache memories.
A traditional method of debug is referred to as background debug mode (BDM). BDM is a static debug process in which a processor is halted in order for a code developer to perform debug operations. A code developer may set break points for stopping the processor at specific points, or may single step through individual instructions to monitor the progress of the processor and identify problems and bugs. BDM is adequate for some applications but is not sufficient for real-time operations, including dynamic adjustment or calibration. Also, certain debug operations require that the application code be tested and corrected without stopping an embedded core processor. For example, an embedded processor system for controlling the engine of an automobile is usually debugged while the engine is running so that halting the core processor is not an option as it would effectively result in stopping the engine.
Dynamic debug methods are being developed to monitor processor operation without halting the processor. In those cases where the physical bus from the cache is externally available, it is not practical or feasible to also externally provide the core processor bus because it would result in an inordinate number of pins of the embedded processor. It is contemplated to develop a debug interface that monitors the processor bus and that provides messages via an internal auxiliary bus or port. Dynamic debug by monitoring the address and data buses between the core processor and cache can be a power-consuming and intrusive process. The bus between the cache and core processor is often referred to as a xe2x80x9cvirtualxe2x80x9d bus. Large buffers coupled to the virtual bus cause bus loading, which can effect the performance of the embedded processor system. Further, the dynamic process of monitoring the address and data bus signals and providing corresponding messages to the external auxiliary bus consumes valuable power. Portable communication devices are typically hand-held and battery operated, and predominately use embedded processor systems. Such portable communication devices include, for example, personal digital assistant, (PDA), cell phones, pagers, global positioning (GPS) modules, etc. It is essential in such portable communication devices to minimize power consumption to conserve battery life.
It is equally important to minimize power consumption in systems which perform dynamic calibration during normal system operation. Automotive applications are an important example of this requirement. For example, in certain automotive applications, real-time calibration (constant) tuning requires the debug module to function as the processor and application are running. Minimizing power consumption of the embedded system is strongly desired.
It is desired to perform dynamic debug in a manner which minimizes power consumption and performance impact due to bus loading on the embedded processor system.